A window to work in
Run a testbench, watch its output and its waves as they happen, pause, run on, restart. Records, arrays, enumerations, fixed and floating point: every signal shows as VHDL writes it.
JanusHDL is an HDL simulator written from scratch from the IEEE standards. It runs VHDL-1993 to VHDL-2019 designs and their testbenches, with PSL, compiles them to native code, and shows every signal in its own waveform viewer. Verilog and SystemVerilog come next. Free, for Windows and Linux, on x86-64 and ARM, Raspberry Pi included.
Run a testbench, watch its output and its waves as they happen, pause, run on, restart. Records, arrays, enumerations, fixed and floating point: every signal shows as VHDL writes it.
Written rule by rule from the IEEE standards, not from anyone's habits, and tested against them.
Every version of the language, including the VHDL-2019 additions, and PSL assertions in VHDL or in comments.
Testbench code compiled to machine code as it runs, with the interpreter as the exact reference behind it.
A waveform viewer that opens recordings while they are still being written, and shows records, arrays and every radix from binary to floating point.
Errors and warnings as you type, go to definition, hover and references in your editor, from the same analyzer that simulates.
Command-line front ends for the commands your flow already calls: your scripts run as they are.
UVVM, OSVVM and VUnit testbenches run as they are, from their own sources. Compile UVVM or OSVVM once, and every run finds them.
A simulator is only useful if you can trust what it tells you. So correctness comes first, and is measured, on every change.
Every change to the simulator runs them: 6,867 Open Logic tests, 1,338 of VUnit's own, OSVVM's 314, UVVM's 193 and its demos, all passing; and 3,652 of the 3,657 cases of the VHDL-93 conformance suite.
Code the standard forbids is reported with its clause and how to fix it. Old code that relies on it still runs, one switch away (--compat).
The compiled code is checked against the interpreter on every change: the same values, the same messages, the same failures.
The same design gives the same result on every run and every machine. Races between processes show up instead of hiding (--order-seed).
Testbench code is compiled to machine code while it runs, on by default. Built for long UVVM and OSVVM regressions as much as for small RTL tests.
A 5 GB recording of 1.8 billion value changes opens in under 4 seconds and stays under 1 GB of memory: the viewer reads only what the screen shows, so the waveforms of a long run open on an ordinary laptop.
For anyone and any use, commercial work included. No licence server, no account, no install: unzip and run, offline if you like.
compat/ take the commands your scripts already call.Unzip, add bin to your path, run.
jhdl counter.vhd counter_tb.vhd --top counter_tb
jhdl -f project.f --top mylib.tb --stop-time 10us --wave run.jhw
jhdlw run.jhwJanus is the Roman god of beginnings, gates, transitions, time, duality, doorways, passages, frames and endings, and he has two faces: one looking forward, one looking back. The same words describe a simulation. It begins at time zero; gates switch; signals make their transitions and pass through the doorways of ports and the passages of the hierarchy, frame by frame in time, until the testbench ends with its verdict. And, like Janus, it looks both ways: it runs your design forward in time, and lets you look back at every value it had.
JanusHDL wants to support it. Get in touch with Rune Bæverrud on LinkedIn.
New to JanusHDL? Ways to work with JanusHDL shows which way fits what you do: the window, the command line, your own scripts or editor.